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eMMC+LPDDR2 H9TP32A4GDMCPR-4GB+4Gb\1.8V\2.8V+1.8V


介绍

4GB eMMC + 4Gb LowPower  DDR2

特性

[ e-NAND Flash ]
● Packaged NAND flash memory with
MultiMediaCard interface
● High capacity memory access
● eMMC/MultiMediaCard system specification,
compliant with V4.41
● Full backward compatibility with previous
MultiMediaCard system specification
● Bus mode
- High-speed MultiMediaCard protocol.
- Three different data bus widths:
1 bit, 4 bits,8 bits.
- Data transfer rate: up to 104Mbyte/s
- DDR mode supported
● Operating voltage range:
- VCCQ = 1.7~1.95V/2.7V~3.6V
- VCC = 3.3V
● Error free memory access
- Internal error correction code
- Internal enhanced data management
algorithm (wear levelling, bad block
management, garbage collection)
- Possibility for the host to make sudden
power failure safe-update operations for
data content
● Security
- Password protection of data
- Security Erase
- Security Trim
- Secure bad block management
- Built-in write protection
● Boot
- Simple boot sequence method
● Power saving
- Enhanced power saving method by
introducing sleep functionality
● Partition management with enhanced storage.
● Hardware reset supported

[ LPDDR2 S4B ]
● VDD1 = 1.8V (1.7V to 1.95V)
● VDD2, VDDCA and VDDQ = 1.2V (1.14V to 1.30)
● HSUL_12 interface (High Speed Unterminated Logic
1.2V)
● Double data rate architecture for command, address
and data Bus;
- all control and address except CS_n, CKE latched at
both rising and falling edge of the clock
- CS_n, CKE latched at rising edge of the clock
- two data accesses per clock cycle
● Differential clock inputs (CK_t, CK_c)
● Bi-directional differential data strobe (DQS_t, DQS_c)
- Source synchronous data transaction aligned to bi-directional
differential data strobe (DQS_t, DQS_c)
- Data outputs aligned to the edge of the data strobe
(DQS_t, DQS_c) when READ operation
- Data inputs aligned to the center of the data strobe
(DQS_t, DQS_c) when WRITE operation
● DM masks write data at the both rising and falling edge
of the data strobe
● Programmable RL (Read Latency) and WL (Write Latency)
● Programmable burst length: 4, 8 and 16
● Auto refresh and self refresh supported
● All bank auto refresh and per bank auto refresh supported
● Clock Stop Mode
● Auto TCSR (Temperature Compensated Self Refresh)
● PASR (Partial Array Self Refresh) by Bank Mask and
Segment Mask
● DS (Drive Strength)
● DPD (Deep Power Down)
● ZQ (Calibration)

生产厂商:Hynix

datasheet:

H9TP32A4GDMCPR_Series_(Rev0.2).pdf
下载: pdf 文件
 

 


 
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