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蓝牙控制器BlueCore6\BTv2.1EDR

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特性:

Fully qualified Bluetooth v2.1 + EDR specification
Piconet and scatternet support
Minimum external components
Low-power 1.5V operation, 1.8V to 3.6V I/O
Integrated 1.5V regulator
Integrated CODEC offering significant power reduction over the CVSD‑based
Support for 802.11 coexistence
Green (RoHS and no antimony or halogenated flame retardants)

Radio
• Common TX/RX terminal simplifies external
matching; eliminates external antenna switch
• No external trimming is required in production
• Bluetooth v2.1 + EDR specification compliant
Transmitter
• 9dBm (0.5mm pitch WLCSP package), 8dBm (QFN
package) or 7dBm (Ultrathin WLCSP and WLCSP
package) RF transmit power with level control from
on-chip 6-bit DAC over a dynamic range >30dB
• Class 1 (0.5mm pitch WLCSP and QFN package),
Class 2 and Class 3 support without the need for an
external power amplifier or TX/RX switch
Receiver
• Receiver sensitivity of -90dBm
• Integrated channel filters
• Digital demodulator for improved sensitivity and
cochannel rejection
• Real-time digitised RSSI available on HCI interface
• Fast AGC for enhanced dynamic range
• Channel classification for AFH
Synthesiser
• Fully integrated synthesiser requires no external
VCO varactor diode, resonator or loop filter
• Compatible with crystals between 16 and 26MHz or
an external clock between 12 and 52MHz
Baseband and Software
• CODEC (16, 24, 32, 40 kbps) offers significant
power reduction over the CVSD based system when
used at both ends of the link
• Internal 48KB RAM, allows full speed data transfer,
mixed voice and data, and full piconet operation,
including all EDR packet types
• Logic for forward error correction, header error
control, access code correlation, CRC, demodulation,
encryption bit stream generation, whitening and
transmit pulse shaping. Supports all Bluetooth v2.1 +
EDR features including eSCO and AFH
• Transcoders for A-law, mu-law and linear voice from
host and A-law, μ-law and CVSD voice over air
Auxiliary Features
• Clock request output to control an external clock
• Device can run in low power modes from an external
32768Hz clock signal
• Power management includes digital shutdown, and
wake up commands with an integrated low power
oscillator for ultra low power Park/Sniff/Hold mode
• Auto Data Rate setting, subject to host interface in
use
• On-chip linear regulators:
⚬ 1.8V output from 2.7V to 5.5V input to power I/O
ring (load current 100mA)
⚬ Low dropout linear regulator producing 1.5V core
voltage from 1.8V
• Power-on-reset cell detects low supply voltage
• Arbitrary sequencing of power supplies permitted
Physical Interfaces
• SDIO and CSPI
• SPI interface up to 4Mbaud for system debugging
• UART interface with programmable baud rate up to
4Mbaud
• Bidirectional serial programmable audio interface,
supporting PCM and I2S formats
Bluetooth Stack
 

 
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