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八位并行输入/串行输出移位寄存器74HC165


介绍

The MM54HC165/MM74HC165 high speed PARALLEL-IN/
SERIAL-OUT SHIFT REGISTER utilizes advanced silicon-
gate CMOS technology. It has the low power consumption
and high noise immunity of standard CMOS integrated cir-
cuits, along with the ability to drive 10 LS-TTL loads.
This 8-bit serial shift register shifts data from QA to QH when
clocked. Parallel inputs to each stage are enabled by a low
level at the SHIFT/LOAD input. Also included is a gated
CLOCK input and a complementary output from the eighth
bit.
Clocking is accomplished through a 2-input NOR gate per-
mitting one input to be used as a CLOCK INHIBIT function.
Holding either of the CLOCK inputs high inhibits clocking,
and holding either CLOCK input low with the SHIFT/LOAD
input high enables the other CLOCK input. Data transfer
occurs on the positive going edge of the clock. Parallel load-
ing is inhibited as long as the SHIFT/LOAD input is high.
When taken low, data at the parallel inputs is loaded directly
into the register independent of the state of the clock.
The 54HC/74HC logic family is functionally as well as pin-
out compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static dis-
charge by internal diode clamps to VCC and ground.
 

特性

• Typical propagation delay: 20 ns (clock to Q)
• Wide operating supply voltage range: 2±6V
• Low input current: 1 mA maximum
• Low quiescent supply current: 80 mA maximum (74HC Series)
• Fanout of 10 LS-TTL loads

生产厂商:National Semiconductor
 
datasheet:
74HC165.PDF
下载: pdf 文件

 

 
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