The Hynix NAND Flash has 256Mx16bit with spare 8Mx16 bit capacity. The device is offered in 1.8 Vcc Power Supply, and with x16 I/O interface Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased.
The device contains 4096 blocks, composed by 64 pages. A program operation allows to write the 2112-byte page in typical 250us and an erase operation can be performed in typical 2ms on a 128K-byte block.
Data in the page can be read out at 45ns cycle time per byte(x8). The I/O pins serve as the ports for address and data
input/output as well as command input.
This interface allows a reduced pin count and easy migration towards different densities, without any rearrangement of
footprint. Commands, Data and Addresses are synchronously introduced using CE, WE, RE, ALE and CLE input pin. The on-chip Program/Erase Controller automates all read, program and erase functions including pulse repetition, where required, and internal verification and margining of data. The modify operations can be locked using the WP input. The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multiple memories the R/B pins can be connected all together to provide a global status signal.
The copy back function allows the optimization of defective blocks management. When a page program operation fails
the data can be directly programmed in another page inside the same array section without the time consuming serial
data insertion phase. Copy back operation automatically executes embedded error detection operation: 1bit error out of
every 264-word can be detected. Due to this feature, it is no more nor necessary nor recommended to use external 2-bit ECC to detect copy back operation errors. Data read out after copy back read (both for single and multiplane cases) is allowed.
Even the write-intensive systems can take advantage of the Hynix NAND Flash extended reliability of 100K program/erase
cycles by supporting ECC (Error Correcting Code) with real time mapping-out algorithm. The chip supports CE don’t care
function. This function allows the direct download of the code from the NAND Flash memory device by a microcontroller,
since the CE transitions do not stop the read operation.
This device includes also extra features like OTP/Unique ID area, Read ID2 extension, and Block Protection.
Especially Block Protection allows protection on Block 0 or OTP area of the device against Write/Erase operations on that block.
The Hynix mobile DDR SDRAM is 2,147,483,648-bit CMOS Low Power Double Data Rate Synchronous DRAM (Mobile
DDR SDRAM), ideally suited for mobile applications which use the battery such as PDAs, 2.5G and 3G cellular phones
with internet access and multimedia capabilities, mini-notebook, hand-held PCs. It is organized as 4banks of
The Hynix mobile DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data